The occurrence of soft errors in memory is a major reason for failures in the processing of the computing applications. These soft errors often occur due to random incidental radiation that changes the electrical charge in one or more bit cells within the memory. Convention solutions store one or more parity bits along with data to detect such errors but often do not detect and report in a timely fashion sufficient data to provide an error response suitable for timing-critical computing applications.
The problems noted above are solved in large part by a memory system that relatively quickly “scrubs” such errors when possible. The disclosed memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.